1. Field of the Invention
The present invention relates to a non-volatile memory device and method of preventing a hot electron program disturb phenomenon, and more specifically, a method of preventing generation of program disturbance incurred by hot electrons in a NAND flash memory device.
2. Discussion of Related Art
There is an increasing demand for semiconductor memory devices which can be electrically programmed and erased without a refresh function of rewriting data at a predetermined cycle. The term “program” refers to an operation of writing data into memory cells.
In order to increase the level of integration of memory devices, a NAND flash memory device in which a plurality of memory cells is connected in series (i.e., a structure in which neighboring cells share the drain or source) to form one string has been developed. The NAND flash memory device is a memory device that sequentially reads information, unlike a NOR flash memory device.
FIG. 1 is a circuit diagram of a conventional NAND flash memory device. FIG. 2 is a table showing a program voltage condition of the NAND flash memory device shown in FIG. 1.
Referring to FIGS. 1 and 2, a selected bit line BLo is supplied with the ground voltage (0V), a non-selected bit line BLe is supplied with the power supply voltage (VCC), a drain select line DSL is supplied with the power supply voltage (VCC), a source select line SSL is supplied with the ground voltage (0V), a word line WL2 is supplied with a program voltage (Vpgm) of about 16 to 19V, and the remaining word lines WL0, WL1, WL3 to WL31 are supplied with a pass voltage, i.e., a program-prohibit voltage (Vpass) of 8V to 10V. If the aforementioned program voltage condition is fulfilled, data are programmed into a memory cell MC2′.
The NAND flash memory device shown in FIG. 1 has two kinds of disturb modes in a program operation. One mode is Vpass disturb mode and the other mode is Vpgm disturb mode.
In Vpass disturb mode, memory cells MC0′, MC1′, MC3′ to MC31′ are disturbed. These memory cells exist in the same string 12 as the memory cell MC2′ to be programmed. The term “Vpass disturb” refers to a phenomenon in which the memory cells MC0′, MC1′, MC3′ to MC31′ are programmed under the condition in which a voltage of each of the word lines WL0 to WL1 and WL3 to WL31 is 10V and a channel voltage of each of the memory cells MC0′, MC1′, MC3′ to MC31′ is 0V.
In Vpgm disturb mode, the memory cell MC2 is disturbed. This memory cell exists in the same word line WL2 as the cell MC2′ to be programmed. The term “Vpgm disturb” refers to a phenomenon in which the memory cell MC2 is programmed under the condition in which a voltage of the word line WL2 is 18V and a channel voltage of the memory cell MC2 is 8V.
The channel voltage of the memory cells MC0 to MC31 connected to the non-selected bit line BLe to which the power supply voltage (VCC) is applied is all boosted to 8V. This is because the non-selected bit line BLe is supplied with the power supply voltage (VCC) unlike the selected bit line BLo.
One reason why the channel is boosted to 8V will be described below with reference to FIG. 3.
If the non-selected bit line BLe is supplied with the power supply voltage (VCC) and a drain select transistor DST is turned on, a voltage is shifted toward the channels of the memory cells MC0 to MC31 as much as (Vcc-Vt) (where, Vt is the threshold voltage of DST), so that the channel of the memory cells MC0 to MC31 are initially charged with (Vcc-Vt). The drain select transistor DST is then turned off without forming a channel.
Tunnel oxide film capacitance (Cox) and Oxide Nitride Oxide (ONO) capacitance (Cono) exist between the channel of the memory cells MC0 to MC31 and a control gate CG. Depletion capacitance (Cch) exists between the channel and a bulk (a substrate Si-Sub). Therefore, channels Vch0 to Vch31 are boosted to match the coupling of three kinds of capacitance (Cono, Cox, and Cch) equaling about 8V.
The program-prohibit cells MC0 to MC31 connected to the non-selected bit line BLe to which the power supply voltage (Vcc) is supplied are not programmed.
Vpass disturb and Vpgm disturb are factors that have significant influence on the yield of NAND flash memory products.
However, additional disturb phenomena, such as channel boosting disturb and hot electron program disturb, occur as the size of memory cells is reduced to 100 nm or less. The term “channel boosting disturb” refers to a phenomenon in which data are programmed into unwanted memory cells MC0 and MC31 by hot electrons generated as the channels Vch0 to Vch31 of the memory cells MC0 to MC31 are boosted.
The channel boosting disturb phenomenon by these hot electrons is typically generated only in the memory cells MC0, MC31 connected to the edge word lines WL0, WL31 within the non-selected string 11 shown in FIG. 3. Of them, the channel boosting disturb phenomenon is generated in the memory cell MC0 connected to most of the word line WL0.
The channel boosting disturb phenomenon by hot electrons will be described in more detail below with reference to FIG. 3.
A channel Vchs of a source select transistor SST is fixed to a voltage of about 0V by its gate voltage (0V). A channel Vchd of a drain select transistor DST is fixed to a voltage of about 1V by its gate voltage (VCC). However, the channels Vch0, Vch31 of the memory cells MC0, MC31 are boosted to about 8V, as described above.
An electric field of a strong lateral direction (an electric field due to a voltage difference between the channel voltage of 0V of SST and the channel voltage of 8V of MC0) exists between the source select transistor SST and the memory cell MC0. An electric field of a strong lateral direction (an electric field due to a voltage difference between the channel voltage of 1V of DST and the channel voltage of 8V of MC31) also exists between the drain select transistor DST and the memory cell MC31.
One reason why the channel boosting disturb phenomenon by the hot electrons is generally generated in the memory cells MC0 connected to the word line WL0 is that a voltage difference between the channel voltage (Vchs) 0V of the source select transistor SST and the channel voltage (Vch0) 8V of the memory cell MC0 is greater than a voltage difference between the channel voltage (Vchd) 1V of the drain select transistor DST and the channel voltage (Vch31) 8V of the memory cell MC31.
In addition, current of electrons and holes (e-h pair) is generated at the interface between a gate oxide film of the source select transistor SST and a silicon substrate Si-Sub. The holes exit toward the silicon substrate Si-Sub and the electrons move toward the memory cell MC0 along the surface of the silicon substrate Si-Sub. The same phenomenon as those described above is also generated at the interface between the gate oxide film of the source select transistor SST and the silicon substrate Si-Sub.
If the electrons pass through the strong electric field of the lateral direction as described above, the electrons become hot electrons. If these hot electrons are scattered around the memory cells MC0, MC31, the hot electrons are introduced into a floating gate FG of the memory cells MC0, MC31, so that data are programmed into the program-prohibit cells MC0, MC31.
The smaller the size of the memory cells, the stronger the electric field of the lateral direction (since the distance between MC0 and SST or MC31 and DST is narrowed). Therefore, the smaller the size of the memory cells, the more severe the channel boosting disturb phenomenon by hot electrons.
Furthermore, a Multi Level Cell (MLC) flash memory device uses a high program voltage (Vpgm) and a high program-prohibit voltage (Vpass). Therefore, to keep the threshold voltage distribution of the MLC very narrow, the MLC has program pulses, which are 6 times greater than that of a Single Level Cell (SLC). This causes the MLC to have more severe channel boosting disturbance by the aforementioned hot electrons.
FIG. 4 is a view showing that channel boosting disturb by hot electrons has occurred in the memory cells MC0, MC31 connected to the edge word line WL0, WL31.
In FIG. 4, portions illustrated by black lines indicate fail bits.
FIG. 5 is a graph showing the relation between a threshold voltage (Vt) of the cells MC0, MC31 (cells in which channel boosting disturb by hot electrons is generated) and the program-prohibit voltage (Vpass).
From FIGS. 4 and 5, it can be seen that the memory cells MC0, M31 connected to the edge word lines WL0, WL31 have a characteristic quite different from the memory cells MC1 to MC30 connected to other word lines WL1 to WL30.